NVIDIA holds sixty percent of TSMC's CoWoS allocation for 2026. AMD takes another eleven with the MI355 and MI400 line. Google's TPU gets roughly ten, Meta five, OpenAI one. The hyperscaler order book reads like a treaty between empires drawn on a single packaging line.

The roadmap the foundry industry sold from 2017 to 2024 priced the package as a finishing step. Logic was the moat, dies were the asset, the substrate was where the work ended. Every consensus deck on AI capex sat on the assumption that 3nm yield and HBM supply were the binding factors. The press release counted wafers.

CoWoS-L is scaling from thirty-five thousand wafers a month at the close of 2024 to a hundred and thirty thousand by late this year. TSMC is pushing CoW orders out to ASE and Amkor for Vera CPU and automotive packages because the in-house line is booked through 2027. The OSAT that was supposed to finish chips now finishes the chips NVIDIA itself cannot fit on the prime line.

Cap-ex per package crossed cap-ex per wafer this cycle. Bridge die yield, warpage on a fourteen-reticle interposer, copper redistribution that stays planar through thermal cycling. Those are the gates the next H100 successor passes through. The GPU nobody can order in May 2026 is rationed by a square of substrate the industry filed under "back end" until last quarter.